6502 Opcodes

From NES Hacker Wiki
Jump to: navigation, search

This is a list of Opcodes used by the 6502 Microprocessor.

Logical Order, Grouped

Storage

  • LDA - Load A with M
  • LDX - Load X with M
  • LDY - Load Y with M
  • STA - Store A in M
  • STX - Store X in M
  • STY - Store Y in M
  • TAX - Transfer A to X
  • TAY - Transfer A to Y
  • TSX - Transfer Stack Pointer to X
  • TXA - Transfer X to A
  • TXS - Transfer X to Stack Pointer
  • TYA - Transfer Y to A

Math

  • ADC - Add M to A with Carry
  • DEC - Decrement M by One
  • DEX - Decrement X by One
  • DEY - Decrement Y by One
  • INC - Increment M by One
  • INX - Increment X by One
  • INY - Increment Y by One
  • SBC - Subtract M from A with Borrow

Bitwise

  • AND - "AND" M with A
  • ASL - Shift Left One Bit (M or A)
  • BIT - Test Bits in M with A
  • EOR - "Exclusive-Or" M with A
  • LSR - Shift Right One Bit (M or A)
  • ORA - "OR" M with A
  • ROL - Rotate One Bit Left (M or A)
  • ROR - Rotate One Bit Right (M or A)

Branch

  • BCC - Branch on Carry Clear
  • BCS - Branch on Carry Set
  • BEQ - Branch on Result Zero
  • BMI - Branch on Result Minus
  • BNE - Branch on Result not Zero
  • BPL - Branch on Result Plus
  • BVC - Branch on Overflow Clear
  • BVS - Branch on Overflow Set

Jump

  • JMP - Jump to Location
  • JSR - Jump to Location Save Return Address
  • RTI - Return from Interrupt
  • RTS - Return from Subroutine

Registers

  • CLC - Clear Carry Flag
  • CLD - Clear Decimal Mode
  • CLI - Clear interrupt Disable Bit
  • CLV - Clear Overflow Flag
  • CMP - Compare M and A
  • CPX - Compare M and X
  • CPY - Compare M and Y
  • SEC - Set Carry Flag
  • SED - Set Decimal Mode
  • SEI - Set Interrupt Disable Status

Stack

  • PHA - Push A on Stack
  • PHP - Push Processor Status on Stack
  • PLA - Pull A from Stack
  • PLP - Pull Processor Status from Stack

System

  • BRK - Force Break
  • NOP - No Operation


Alphabetical, Grouped

A

  • ADC - Add M to A with Carry
  • AND - "AND" M with A
  • ASL - Shift Left One Bit (M or A)

B

  • BCC - Branch on Carry Clear
  • BCS - Branch on Carry Set
  • BEQ - Branch on Result Zero
  • BIT - Test Bits in M with A
  • BMI - Branch on Result Minus
  • BNE - Branch on Result not Zero
  • BPL - Branch on Result Plus
  • BRK - Force Break
  • BVC - Branch on Overflow Clear
  • BVS - Branch on Overflow Set

C

  • CLC - Clear Carry Flag
  • CLD - Clear Decimal Mode
  • CLI - Clear interrupt Disable Bit
  • CLV - Clear Overflow Flag
  • CMP - Compare M and A
  • CPX - Compare M and X
  • CPY - Compare M and Y

D

  • DEC - Decrement M by One
  • DEX - Decrement X by One
  • DEY - Decrement Y by One

E

  • EOR - "Exclusive-Or" M with A

I

  • INC - Increment M by One
  • INX - Increment X by One
  • INY - Increment Y by One

J

  • JMP - Jump to Location
  • JSR - Jump to Location Save Return Address

L

  • LDA - Load A with M
  • LDX - Load X with M
  • LDY - Load Y with M
  • LSR - Shift Right One Bit (M or A)

N

  • NOP - No Operation

O

  • ORA - "OR" M with A

P

  • PHA - Push A on Stack
  • PHP - Push Processor Status on Stack
  • PLA - Pull A from Stack
  • PLP - Pull Processor Status from Stack

R

  • ROL - Rotate One Bit Left (M or A)
  • ROR - Rotate One Bit Right (M or A)
  • RTI - Return from Interrupt
  • RTS - Return from Subroutine

S

  • SBC - Subtract M from A with Borrow
  • SEC - Set Carry Flag
  • SED - Set Decimal Mode
  • SEI - Set Interrupt Disable Status
  • STA - Store A in M
  • STX - Store X in M
  • STY - Store Y in M

T

  • TAX - Transfer A to X
  • TAY - Transfer A to Y
  • TSX - Transfer Stack Pointer to X
  • TXA - Transfer X to A
  • TXS - Transfer X to Stack Pointer
  • TYA - Transfer Y to A


Alphabetical, Expanded

Opcode

Mode

Hex
ADC Immediate 69
ADC Zero Page 65
ADC Zero Page, X 75
ADC Absolute 6D
ADC Absolute, X 7D
ADC Absolute, Y 79
ADC (Indirect, X) 61
ADC (Indirect), Y 71
AND Immediate 29
AND Zero Page 25
AND Zero Page, X 35
AND Absolute 2D
AND Absolute, X 3D
AND Absolute, Y 39
AND (Indirect, X) 21
AND (Indirect), Y 31
ASL Accumulator 0A
ASL Zero Page 06
ASL Zero Page, X 16
ASL Absolute 0E
ASL Absolute, X 1E
BCC 90
BCS B0
BEQ F0
BIT Zero Page 24
BIT Absolute 2C
BMI 30
BNE D0
BPL 10
BRK 00
BVC 50
BVS 70
CLC 18
CLD D8
CLI 58
CLV B8
CMP Immediate C9
CMP Zero Page C5
CMP Zero Page, X D5
CMP Absolute CD
CMP Absolute, X DD
CMP Absolute, Y D9
CMP (Indirect, X) C1
CMP (Indirect), Y D1
CPX Immediate E0
CPX Zero Page E4
CPX Absolute EC
CPY Immediate C0
CPY Zero Page C4
CPY Absolute CC
DEC Zero Page C6
Opcode

Mode

Hex
DEC Zero Page, X D6
DEC Absolute CE
DEC Absolute, X DE
DEX CA
DEY 88
EOR Immediate 49
EOR Zero Page 45
EOR Zero Page, X 55
EOR Absolute 4D
EOR Absolute, X 5D
EOR Absolute, Y 59
EOR (Indirect, X) 41
EOR (Indirect), Y 51
INC Zero Page E6
INC Zero Page, X F6
INC Absolute EE
INC Absolute, X FE
INX E8
INY C8
JMP Indirect 6C
JMP Absolute 4C
JSR 20
LDA Immediate A9
LDA Zero Page A5
LDA Zero Page, X B5
LDA Absolute AD
LDA Absolute, X BD
LDA Absolute, Y B9
LDA (Indirect, X) A1
LDA (Indirect), Y B1
LDX Zero Page A6
LDX Zero Page, Y B6
LDX Absolute AE
LDX Absolute, Y BE
LDX Immediate A2
LDY Immediate A0
LDY Zero Page A4
LDY Zero Page, X B4
LDY Absolute AC
LDY Absolute, X BC
LSR Accumulator 4A
LSR Zero Page 46
LSR Zero Page, X 56
LSR Absolute 4E
LSR Absolute, X 5E
NOP EA
ORA Immediate 09
ORA Zero Page 05
ORA Zero Page, X 15
ORA Absolute 0D
ORA Absolute, X 1D
Opcode

Mode

Hex
ORA Absolute, Y 19
ORA (Indirect, X) 01
ORA (Indirect), Y 11
PHA 48
PHP 08
PLA 68
PLP 28
ROL Accumulator 2A
ROL Zero Page 26
ROL Zero Page, X 36
ROL Absolute 2E
ROL Absolute, X 3E
ROR Accumulator 6A
ROR Zero Page 66
ROR Zero Page, X 76
ROR Absolute 6E
ROR Absolute, X 7E
RTI 40
RTS 60
SBC Immediate E9
SBC Zero Page E5
SBC Zero Page, X F5
SBC Absolute ED
SBC Absolute, X FD
SBC Absolute, Y F9
SBC (Indirect, X) E1
SBC (Indirect), Y F1
SEC 38
SED F8
SEI 78
STA Zero Page 85
STA Zero Page, X 95
STA Absolute 8D
STA Absolute, X 9D
STA Absolute, Y 99
STA (Indirect, X) 81
STA (Indirect), Y 91
STX Zero Page 86
STX Zero Page, Y 96
STX Absolute 8E
STY Zero Page 84
STY Zero Page, X 94
STY Absolute 8C
TAX AA
TAY A8
TSX BA
TXA 8A
TXS 9A
TYA 98


Hex Order

Hex Opcode

Mode

00 BRK
01 ORA (Indirect, X)
02
03
04
05 ORA Zero Page
06 ASL Zero Page
07
08 PHP
09 ORA Immediate
0A ASL Accumulator
0B
0C
0D ORA Absolute
0E ASL Absolute
0F
10 BPL
11 ORA (Indirect), Y
12
13
14
15 ORA Zero Page, X
16 ASL Zero Page, X
17
18 CLC
19 ORA Absolute, Y
1A
1B
1C
1D ORA Absolute, X
1E ASL Absolute, X
1F
20 JSR
21 AND (Indirect, X)
22
23
24 BIT Zero Page
25 AND Zero Page
26 ROL Zero Page
27
28 PLP
29 AND Immediate
2A ROL Accumulator
2B
2C BIT Absolute
2D AND Absolute
2E ROL Absolute
2F
30 BMI
31 AND (Indirect), Y
32
33
34
35 AND Zero Page, X
36 ROL Zero Page, X
37
38 SEC
39 AND Absolute, Y
3A
3B
3C
3D AND Absolute, X
3E ROL Absolute, X
3F
40 RTI
41 EOR (Indirect, X)
42
43
44
45 EOR Zero Page
46 LSR Zero Page
47
48 PHA
49 EOR Immediate
4A LSR Accumulator
4B
4C JMP Absolute
4D EOR Absolute
4E LSR Absolute
4F
50 BVC
51 EOR (Indirect), Y
52
53
54
55 EOR Zero Page, X
Hex Opcode

Mode

56 LSR Zero Page, X
57
58 CLI
59 EOR Absolute, Y
5A
5B
5C
5D EOR Absolute, X
5E LSR Absolute, X
5F
60 RTS
61 ADC (Indirect, X)
62
63
64
65 ADC Zero Page
66 ROR Zero Page
67
68 PLA
69 ADC Immediate
6A ROR Accumulator
6B
6C JMP Indirect
6D ADC Absolute
6E ROR Absolute
6F
70 BVS
71 ADC (Indirect), Y
72
73
74
75 ADC Zero Page, X
76 ROR Zero Page, X
77
78 SEI
79 ADC Absolute, Y
7A
7B
7C
7D ADC Absolute, X
7E ROR Absolute, X
7F
80
81 STA (Indirect, X)
82
83
84 STY Zero Page
85 STA Zero Page
86 STX Zero Page
87
88 DEY
89
8A TXA
8B
8C STY Absolute
8D STA Absolute
8E STX Absolute
8F
90 BCC
91 STA (Indirect), Y
92
93
94 STY Zero Page, X
95 STA Zero Page, X
96 STX Zero Page, Y
97
98 TYA
99 STA Absolute, Y
9A TXS
9B
9C
9D STA Absolute, X
9E
9F
A0 LDY Immediate
A1 LDA (Indirect, X)
A2 LDX Immediate
A3
A4 LDY Zero Page
A5 LDA Zero Page
A6 LDX Zero Page
A7
A8 TAY
A9 LDA Immediate
AA TAX
AB
Hex Opcode

Mode

AC LDY Absolute
AD LDA Absolute
AE LDX Absolute
AF
B0 BCS
B1 LDA (Indirect), Y
B2
B3
B4 LDY Zero Page, X
B5 LDA Zero Page, X
B6 LDX Zero Page, Y
B7
B8 CLV
B9 LDA Absolute, Y
BA TSX
BB
BC LDY Absolute, X
BD LDA Absolute, X
BE LDX Absolute, Y
BF
C0 CPY Immediate
C1 CMP (Indirect, X)
C2
C3
C4 CPY Zero Page
C5 CMP Zero Page
C6 DEC Zero Page
C7
C8 INY
C9 CMP Immediate
CA DEX
CB
CC CPY Absolute
CD CMP Absolute
CE DEC Absolute
CF
D0 BNE
D1 CMP (Indirect), Y
D2
D3
D4
D5 CMP Zero Page, X
D6 DEC Zero Page, X
D7
D8 CLD
D9 CMP Absolute, Y
DA
DB
DC
DD CMP Absolute, X
DE DEC Absolute, X
DF
E0 CPX Immediate
E1 SBC (Indirect, X)
E2
E3
E4 CPX Zero Page
E5 SBC Zero Page
E6 INC Zero Page
E7
E8 INX
E9 SBC Immediate
EA NOP
EB
EC CPX Absolute
ED SBC Absolute
EE INC Absolute
EF
F0 BEQ
F1 SBC (Indirect), Y
F2
F3
F4
F5 SBC Zero Page, X
F6 INC Zero Page, X
F7
F8 SED
F9 SBC Absolute, Y
FA
FB
FC
FD SBC Absolute, X
FE INC Absolute, X
FF


Simplified

  • BRK/JSR/RTI/RTS: 0II0 0000 (II = BRK (0), JSR (1), RTI (2), or RTS (3))
  • BIT: 0010 M100 (M = Zero Page (0) or Absolute (1))
  • JMP: 01M0 1100 (M = Absolute (0) or Indirect (1))
  • Unused unless listed above: 0??? ?100
  • Branch N/V/C/Z: MMS1 0000 (MM = Flag Type, S = Status)
  • PHP/PLP/PHA/PLA: 0AP0 1000 (A = Processor Status (0) or Accumulator (1), P = Push (0) or Pull (1))
  • CL?/SE?: MMS1 1000 (MM = Flag Type (C/I/V/D), S = Status; SEV doesn't exist, and CLV is set to B8 instead)
  • INY/INX: 11V0 1000
  • STY/LDY: 10LM MM00
  • CPY/CPX: 11VM MM00
  • Modes:
    • 000 - Immediate: M = Op1 (not used for STX)
    • 001 - Zero Page: M = (Op1)
    • 010 - Accumulator: M = A for LDY (88 is DEY instead, INY/INX overrides this)
    • 011 - Absolute: M = (Op2)
    • 100 - not used because of Branch stuff
    • 101 - Zero Page, X: (X+Op1) (only used for STY/LDY; D4 and F4 are blank)
    • 110 - Accumulator: M = A for STY (B8, D8, and F8 are all used for flag stuff instead)
    • 111 - Absolute, X: (Op2+X) (only used for LDY; 9C, DC, and FC are all blank)
  • OR/AND/EOR/ADC A, M: 0CCM MM01 (CC = Instruction, MMM = Mode)
  • ST/LD/CMP/SBC A, M: 1CCM MM01
  • Modes:
    • 000 - (Indirect, X): M = ((X+Op1))
    • 001 - Zero Page: M = (Op1)
    • 010 - Immediate: M = Op1
    • 011 - Absolute: M = (Op2)
    • 100 - (Indirect), Y: M = (Y+(Op1))
    • 101 - Zero Page, X: (X+Op1)
    • 11X - Absolute, Y/X: (Op2+Y/X)
  • ASL/ROL/LSR/ROR: 0DRM MM10 (D = Direction: Left = 0, Right = 1; R = Shift (0) or Rotate (1); MMM = Mode)
  • STX/LDX: 10LM MM10
  • DEC/INC: 11PM MM10
  • Modes:
    • 000 - generally unused
    • 001 - Zero Page: M = (Op1)
    • 010 - Accumulator: M = A (A substituted with X in DEC/INC instead)
    • 011 - Absolute: M = (Op2)
    • 100 - never used
    • 101 - Zero Page, X: (X+Op1) (X substituted with Y in STX/LDX)
    • 111 - Absolute, X: (Op2+X) (X substituted with Y in STX/LDX)
  • 1010 0010 - LDX Immediate; noted because otherwise, ???? 0010 is never used
  •  ???? ??11 - always never used

Execution Time

 


Accu-
mula-
tor



Imme-
diate



Zero
Page


Zero
Page
X


Zero
Page
Y



Abso-
lute


Abso-
lute
X


Abso-
lute
Y



Imp-
lied



Rela-
tive


(In-
direct
X)


(In-
direct)
Y

Abso-
lute
In-
direct

ADC . 2 3 4 . 4 4* 4* . . 6 5* .
AND . 2 3 4 . 4 4* 4* . . 6 5* .
ASL 2 5 6 . 6 7 . . . . . .
BCC . . . . . . . . . 2† . . .
BCS . . . . . . . . . 2† . . .
BEQ . . . . . . . . . 2† . . .
BIT . . 3 . . 4 . . . . . . .
BMI . . . . . . . . . 2† . . .
BNE . . . . . . . . . 2† . . .
BPL . . . . . . . . . 2† . . .
BRK . . . . . . . . 7 . . . .
BVC . . . . . . . . . 2† . . .
BVS . . . . . . . . . 2† . . .
CLC . . . . . . . . 2 . . . .
CLD . . . . . . . . 2 . . . .
CLI . . . . . . . . 2 . . . .
CLV . . . . . . . . 2 . . . .
CMP . 2 3 4 . 4 4* 4* . . 6 5* .
CPX . 2 3 . . 4 . . . . . . .
CPY . 2 3 . . 4 . . . . . . .
DEC . . 5 6 . 6 7 . . . . . .
DEX . . . . . . . . 2 . . . .
DEY . . . . . . . . 2 . . . .
EOR . 2 3 4 . 4 4* 4* . . 6 5* .
INC . . 5 6 . 6 7 . . . . . .
INX . . . . . . . . 2 . . . .
INY . . . . . . . . 2 . . . .
JMP . . . . . 3 . . . . . . 5
JSR . . . . . 6 . . . . . . .
LDA . 2 3 4 . 4 4* 4* . . 6 5* .
LDX . 2 3 . 4 4 . 4* . . . . .
LDY . 2 3 4 . 4 4* . . . . . .
LSR 2 . 5 6 . 6 7 . . . . . .
NOP . . . . . . . . 2 . . . .
ORO . 2 3 4 . 4 4* 4* . . 6 5* .
PHA . . . . . . . . 3 . . . .
PHP . . . . . . . . 3 . . . .
PLA . . . . . . . . 4 . . . .
PLP . . . . . . . . 4 . . . .
ROL 2 . 5 6 . 6 7 . . . . . .
ROR 2 . 5 6 . 6 7 . . . . . .
RTI . . . . . . . . 6 . . . .
RTS . . . . . . . . 6 . . . .
SBC . 2 3 4 . 4 4* 4* . . 6 5* .
SEC . . . . . . . . 2 . . . .
SED . . . . . . . . 2 . . . .
SEI . . . . . . . . 2 . . . .
STA . . 3 4 . 4 5 5 . . 6 6 .
STX . . 3 . 4 4 . . . . . . .
STY . . 3 4 . 4 . . . . . . .
TAX . . . . . . . . 2 . . . .
TAY . . . . . . . . 2 . . . .
TSX . . . . . . . . 2 . . . .
TXA . . . . . . . . 2 . . . .
TXS . . . . . . . . 2 . . . .
TYT . . . . . . . . 2 . . . .

* Add one cycle if indexing across page boundary
† Add one cycle if branch is taken, and one additional if branching operation crosses page boundary